Very High Speed, Time Domain, Analog-to-Digital Converter

December 12, 2024

Motivated by advances in technology and high-speed communications, serializers-deserializers, which require analog-to-digital converters in the receiver, operate with frequencies in excess of 100 GSa/s. Such high frequencies can only be achieved by time interleaving multiple converters, each operating at a lower rate, which impacts area and power overhead. Recent advancements in semiconductor technology favor digital over analog circuits, particularly in terms of speed and power efficiency. To address this trend, time-mode signal processing circuits have emerged as a promising solution to replace analog blocks with digital alternatives. Voltage-to-time converters encode voltage amplitude signal information as a time interval between events. Time-to-digital converters can then translate the time information into bits. These architectures not only take advantage of the most recent nodes' benefits but also show very promising results in terms of frequency and power consumption, comparable to and even exceeding the voltage domain achievements. The present work studies time-domain architectures and concludes with a proposed analog-to-digital converter of 7-bit, operating at 5 GHz. A common mode dual ramp generator with a single current source voltage-to-time converter followed by a successive approximation register time-to-digital converter using selective delay tuning cells achieves a 6.5-bit ENOB with a TDH = -46.38 dB consuming 12.54 mW, concluding a Walden figure of merit FOM_W of 27.71 fJ/conv. Expected problems, possible solutions, and circuit improvements are also stated.

Authors in the community:

• 

  D

  Diogo Matos Ferreira

  ist196189

Supervisors of this institution:

• 

  J

  Jorge Manuel Dos Santos Ribeiro Fernandes

  ist13276

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico