Performance Monitoring and Event-based Sampling for RISC-V

12/04/2023

Increased attention to RISC-V open Instruction Set Architecture (ISA), has fueled its move from embedded devices to the high-performance computing arena, with the proliferation of RISC-V-based accelerators. However, the absence of powerful performance monitoring tools often results in poorly optimized applications and, consequently, limited computing performance. While the RISC-V ISA already defines a Hardware Performace Monitor and offers support for the Linux perf_events subsystem, research and development on RISC-V-based devices have been more focused on architectures and compilers rather than tools to support monitoring performance. To overcome this limitation, the introduction of PAPI library support for RISC-V processors is proposed in this thesis, and a Precise Event Sampling system specification compatible with future PAPI integration is presented along with a minimal implementation proof-of-concept. The conducted testing and evaluation of the PAPI port were carried out on a SiFive Unmatched board, but the proposed changes, and the corresponding implementation, are easily portable to other systems. The proof of concept for RISC-V Precise Event Sampling was implemented on a CVA6 processor. It was found that, when compared to directly using perf_events, PAPI presents a large overhead; 83360µs in comparison with perf_events 100.24µs. Nevertheless, most of it (81200µs) is concentrated in the initialization of the library, which only occurs once per program execution.

Authors in the community:

• 

  T

  Tiago Alfredo Lopes Rocha

  ist190194

Supervisors of this institution:

• 

  N

  Nuno Filipe Simões Santos Moraes Neves

  ist157949

• 

  P

  Pedro Filipe Zeferino Tomás

  ist146645

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico