Universal Verification Methodology for Power Management Unit

11/30/2022

Nowadays, mixed signal applications are widespread in the semiconductor industry. Mixed signal validation adds complexity to the verification process, which difficults functional verification Universal Verification Methodology (UVM) is the current standard methodology for verifying digital and mixed-signal designs. Real Number Modelling allows the description of mixed-signal designs using a High-level verification language. This approach imposes limitations upon the verification process but builds the foundation for coverage-driven verification and functional verification. Universal Verification Methodology applied to models based on Real Number Modelling allows for robust verification environments while significantly reducing simulation time and time-to-market. In this work, a UVM testbench environment is proposed for voltage regulators and a power management unit verification, under the scope of pAvIs project. This new verification solution is integrated in the design and test flow of SiliconGate.

Authors in the community:

• 

  M

  Marcio Éder Sequeira Soares

  ist188151

Supervisors of this institution:

• 

  M

  Marcelino Bicho dos Santos

  ist13261

• 

  J

  Jorge Manuel Dos Santos Ribeiro Fernandes

  ist13276

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico