Evaluation of Real Time Operating System in RISC-V

06/26/2024

The RISC-V instruction set architecture has emerged as in the community due to its open and royalty-free nature, simplicity, and modularity. System-on-Chip (SoC) implementations based on RISC-V processors can be extended with hardware accelerators to improve the performance of embedded systems by offloading heavy computational tasks from the processor. Using a Real-Time Operating System (RTOS) is essential in meeting the timing requirements and efficiently managing multiple tasks. In this thesis, the SweRVolf SoC was extended to connect to a hardware accelerator. Three scenarios were proposed for managing the hardware accelerator using Zephyr RTOS mechanisms that enable the RISC-V processor to execute different tasks, while the accelerator works in parallel. In the first scenario, a single thread accesses to the accelerator and a semaphore is used to block the thread while it’s working. The second scenario has several threads competing to access the accelerator and semaphores control access attempts. The third scenario uses a thread responsible for managing the accelerator's access. Computational threads send requests to the manager thread to use the accelerator. To evaluate these scenarios, two use case applications were developed and executed on the FPGA board Nexys A7, a set of matrices multiplications and a neural network to predict the digits of the MNIST dataset. The execution times of the different scenarios show that using a manager thread is more time-efficient than the multiple threads competing for access to the accelerator, while providing a larger control over what thread uses the accelerator.

Authors in the community:

• 

  R

  Rui Silva Ferreira

  ist193178

Supervisors of this institution:

• 

  P

  Paulo Ferreira Godinho Flores

  ist12857

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico