Scalable FPGA-based controller of a thousand-ASIC system in the CERN CMS HGCAL detector

Pedro Martim Duarte Rosado

Key information

Authors:

Pedro Martim Duarte Rosado (Martim Rosado)

Supervisors:

Nuno Filipe Valentim Roma (Nuno Filipe Valentim Roma); André David Tinoco Mendes (André David Tinoco Mendes)

Published in

11/11/2022

Abstract

The upcoming of the European Organization for Nuclear Research (CERN) High-Luminosity Large Hadron Collider (LHC) (HL-LHC) phase motivates the replacement of the endcap calorimeters of the Compact Muon Solenoid (CMS) detector with the High-Granularity Calorimeter (HGCAL). To read out its 6 million channels, the HGCAL uses a complex electronic readout chain that comprises a front-end and a back-end. The front-end is located in the experimental cavern comprising about 150 000 radiation-tolerant Application Specific Integrated Circuits (ASICs). The back-end is shielded from radiation and consists of about 100 Field Programmable Gate Arrays (FPGAs). Each FPGA is connected to 108 optical links, each providing a 10.24 Gbit/s transmission rate, and is responsible for configuring up to 3500 ASICs. This dissertation reports on the work contributed to the control system implemented in the back-end of HGCAL to configure the front-end electronics, known as asynchronous (slow) control. By using development boards to emulate the HGCAL hardware still under development, it was possible to prototype the slow control FPGA hardware and validate the communication with the target front-end ASICs while ensuring complete portability between the prototype and the final detector systems. Furthermore, the configuration time of all the HGCAL electronics was roughly estimated at around 1 minute. Another contribution of this work to HGCAL is the design of an accumulator system to accelerate the computation of the mean and standard deviation of several metrics in the testing of the HGCAL Readout Chip (HGCROC) ASIC, allowing up to four times faster analysis in testing.