Master's Thesis
LAYGEN II - Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation
2012
—Key information
Authors:
Supervisors:
Published in
05/14/2012
Abstract
The work presented in this report belongs to the scientific area of electronic design automation and addresses the automatic generation of analog IC layout. An innovative design automation tool based on template descriptions and on evolutionary computation techniques, LAYGEN II, which stems from LAYGEN, was developed to validate the proposed approach giving special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. The designer specifies the sized circuit-level structure, the required technology and, also, provides the technology independent high-level layout guidelines through an abstract layout description, henceforward called template. The generation proceeds in the traditional way, first placement and then routing. For placement, the topological relations present in the template are mapped to a non-slicing B*-tree layout representation, and the tool automatically merge devices and ensures that the design rules are fulfilled. The router optimization kernel consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II, and uses a built-in DRC as evaluation engine. The automatic layout generation is here demonstrated using the LAYGEN II tool for two selected typical analog circuit structures, namely, a fully-dynamic comparator and a single-ended folded cascode amplifier. The layouts were generated for two design processes, UMC 130 nm and AMS 350 nm, and the output provided is a GDSII stream format, a file standard for data exchange of IC layout. The results were validated using the industrial grade verification tool Calibre® to run DRC, LVS, and also extraction, in addition post-layout simulations were successfully performed.
Publication details
Authors in the community:
Ricardo Miguel Ferreira Martins
ist156593
Supervisors of this institution:
Jorge Manuel Correia Guilherme
ist402701
Nuno Cavaco Gomes Horta
ist13947
Fields of Science and Technology (FOS)
electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering
Publication language (ISO code)
eng - English
Rights type:
Embargo lifted
Date available:
02/28/2013
Institution name
Instituto Superior Técnico