Runtime-adaptable cache architecture for modern processors

December 3, 2024

High-performance processing systems must balance data processing with memory access latency to avoid performance bottlenecks as well as excess power consumption. Processor manufacturers address this by optimizing cache hierarchies to reduce cache misses and memory latency. However, traditional caches are static and unable to adapt to specific memory access patterns, either of particular applications or their distinct phases. For instance, caching unsuitable data structures can lead to cache pollution by evicting valuable, reusable data. Additionally, different application phases may vary in their reuse of data structures and exploitation of temporal and spatial locality, resulting in changing cache demands. Recent research on adaptable cache architectures shows promise but often limits reconfiguration flexibility to avoid coherence issues, and overlooks the impact of modern prefetching. This thesis seeks to advance adaptable cache designs by identifying their limitations and exploring options for performance-oriented reconfiguration. Key objectives include mechanisms for reconfiguration, coherence maintenance, and cache autonomy. Experimental evaluations with and without prefetching, as well as varying adaptability constraints, demonstrate that the proposed architecture maintains performance, optimizes low-demand phases, and achieves up to 16% in cache power savings.

Authors in the community:

• 

  A

  Alexandre Carlos Martins Ruivo Correia

  ist193000

Supervisors of this institution:

• 

  N

  Nuno Filipe Simões Santos Moraes Neves

  ist157949

• 

  P

  Pedro Filipe Zeferino Tomás

  ist146645

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico