Stream-based Coarse-Grained Reconfigurable Accelerator

João Francisco Batista Maia

Key information

Authors:

João Francisco Batista Maia (João Francisco Batista Maia)

Supervisors:

Pedro Filipe Zeferino Aidos Tomás (Pedro Filipe Zeferino Tomás); Nuno Filipe Valentim Roma (Nuno Filipe Valentim Roma)

Published in

June 25, 2025

Abstract

This thesis introduces a stream-based dataflow reconfigurable accelerator architecture based on Coarse-Grained Reconfigurable Architectures (CGRAs) for high-performance computing and energy efficiency. The architecture decouples memory accesses from computation through a dedicated streaming engine based on the Unlimited Vector Extension streaming paradigm to efficiently handle affine memory patterns and support complex multi-dimensional loops. Integration with a RISC-V-based system-on-chip using the Chipyard framework enables a comprehensive evaluation. An end-to-end compilation toolchain was developed to automate the dataflow graph extraction, streaming pattern identification, and CGRA mapping. The architecture was synthesized in a 7 nm technology node to assess its performance and efficiency. While direct evaluation revealed only modest performance and efficiency improvements, the conducted analysis identified key limitations in the existing streaming engine implementations and mapping tools. Proposed enhancements to these components were estimated to yield substantial performance and energy efficiency gains, demonstrating the architecture's promising potential. These findings underscore the value of stream-driven reconfigurable dataflow architectures as a highly viable platform for computation-intensive applications while highlighting the importance of robust streaming and mapping solutions. The proposed improvements lay a foundation for future research to fully realize the system's capabilities in delivering competitive energy-efficient performance.