AAC audio decoder using a RISC-V processor and hardware accelerators

June 26, 2026

Advanced Audio Coding (AAC) is a widely used audio compression standard. Embedded systems often require AAC decoding solutions that meet real-time constraints. This thesis presents an Intellectual Property (IP) core for AAC Low Complexity (AAC-LC) decoding. The proposed solution is based on the IOb-System platform, the VexRiscv processor, and the FDK-AAC library. The decoder supports two operating modes: a Memory-to-Memory configuration for applications where the complete AAC-LC bitstream is stored in memory, and a Stream configuration for real-time decoding of progressively received frames. The performance of the Memory-to-Memory configuration was improved through three enhancements: a modification to the write-path logic of the Advanced eXtensible Interface (AXI) crossbar, changes to the processor configuration, and the addition of a custom count-leading-zero (CLZ) instruction. The proposed decoder was implemented on an FPGA and operated at a system clock frequency of 83 MHz. The final Memory-to-Memory configuration achieved worst-frame decode times between 10 ms and 19 ms, satisfying the real-time requirement for the tested bitstreams with a sampling rate of 44.1 kHz. The Stream configuration achieved worst-frame decode times between 9 ms and 20 ms, satisfying the real-time requirement for the tested bitstreams with sampling rates of 44.1 kHz and 48 kHz.

Authors in the community:

• 

  A

  André Gonçalo Belim Nóbrega

  ist196155

Supervisors of this institution:

• 

  J

  José João Henriques Teixeira de Sousa

  ist13090

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

eng - English

Instituto Superior Técnico