Using variational autoencoders to address the inverse sizing design problem of analog integrated circuits

December 23, 2025

This thesis introduces a generative modeling framework based on Variational Autoencoder to address the inverse sizing design issue in Analog ICs. Three model architectures are proposed: fully-connected artificial neural network encoders and decoders trained with the standard VAE objective, an alternative pipeline where the ANN encoder is replaced by a self-attention mechanism, and a hierarchical VAE that improves model expressiveness through polynomial feature expansion and data augmentation strategies. Experimental results indicate that our approach not only outperforms traditional supervised learning techniques but also reveals that the hierarchical VAE exhibits superior extrapolation capabilities by generating a performance cloud that extends well beyond the training distribution while keeping error growth below 24%, thereby surpassing the performance of the DDPM model. Furthermore, the VAE’s generative nature enables it to sample multiple feasible solutions within the target performance region, demonstrating enhanced diversity and controllability.

Authors in the community:

• 

  H

  Han Liu

  ist1111978

Supervisors of this institution:

• 

  R

  Ricardo Miguel Ferreira Martins

  ist156593

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

por - Portuguese

Instituto Superior Técnico