Understanding Performance Non-Deterministic Factors of Multi-Core Processors

Diogo Manuel Da Rosa Cochicho

Key information

Authors:

Diogo Manuel Da Rosa Cochicho (Diogo Manuel Da Rosa Cochicho)

Supervisors:

Pedro Filipe Zeferino Aidos Tomás (Pedro Filipe Zeferino Tomás); Nuno Filipe Valentim Roma (Nuno Filipe Valentim Roma)

Published in

July 2, 2025

Abstract

This thesis investigates performance unpredictability in Commercial off‑the‑Shelf (COTS) multicore processors (MCPs), a critical barrier to their certification for avionics and other real‑time safety‑critical domains. The study focuses on hardware interference channels within the data path between the load/store unit of the Application Processing Unit (APU) and main memory, which introduce timing variability when multiple cores compete for shared resources such as caches, interconnects, and memory controllers. To address this challenge, a bare‑metal benchmarking framework—Metal Profiler—was developed to automate the generation, deployment, and analysis of memory stress tests. This tool enables systematic exploration of interference scenarios across two representative platforms: the AMD Zynq™ Ultrascale+™ MPSoC and the Raspberry Pi 4 Model B. By isolating software noise, Metal Profiler accurately characterizes worst‑case degradation and facilitates parameterized testing of shared hardware components. Two mitigation strategies were implemented and assessed: Cache Coloring, which partitions shared cache resources spatially, and a simplified Bandwidth Limiter, which regulates memory traffic to prevent buffer saturation. Experimental results demonstrate that interference can induce substantial performance degradation, but also that prior studies likely overstated its impact due to software‑layer effects. The findings refine the understanding of MCP interference in safety‑critical environments, showing that bare‑metal characterization yields more precise insights and that mitigation methods like cache partitioning are more effective than previously reported. This work provides a foundation for future certification efforts and contributes tools and methodologies for improving timing predictability in multicore‑based avionics systems.