Better concurrent programming by exploiting the new support for hardware transactional memory in Intel processors

José Miguel Leitão de Oliveira Esteves

Key information

Authors:

José Miguel Leitão de Oliveira Esteves (José Miguel Leitão de Oliveira Esteves)

Supervisors:

João Pedro Faria Mendonça Barreto (João Pedro Faria Mendonça Barreto)

Published in

June 5, 2025

Abstract

The landscape of concurrent programming has evolved significantly with the introduction of Transactional Memory (TM). TM has attained scholar's attention for enabling optimistic concurrency, because it enhances scalability and performance, and also reduces the complexity associated with synchronizing memory access for programmers. Hardware Transactional Memory (HTM) emerges as a promising hardware-embedded technology to achieve greater performance because of its nature. By leveraging the hardware architecture, HTM implements a TM system with reduced overheads and minimized computational costs for transaction-related operations. In response to the growing demand for high-performance computing, Intel developed its own HTM implementation in commercially available processors, named Intel TSX. Furthermore, recently the ability to suspend and resume a transaction's load track was added to Intel TSX. Previous studies have concluded that suspend/resume can add tangible benefits, as these instructions enable intricate synchronization systems that are capable of supporting Uninstrumented Read-Only transactions. The design of these solutions targets read-dominated workloads, as they represent an amountable portion of real-world workloads. With inspiration drawn from previous research, this work introduces Extended Transactional Synchronization for Transactional Memory (XTS-TM) a brand new extension for Intel TSX that leverages suspend/resume to extract performance from HTM. This work presents an extended assessement on suspend/resume's and XTS-TM's performance, which highlights workloads where this solution is able to outperform the baseline HTM-SGL implementation of Intel TSX.