Article

MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications

2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Moradi Cherati, Sahar; Sousa, Leonel — 2025 — IEEE

Key information

Authors:

Moradi Cherati, Sahar (Sahar Moradi Cherati); Sousa, Leonel (Leonel Augusto Pires Seabra de Sousa)

Published in

August 27, 2025

Abstract

Edge computing applications, such as IoT and wearable devices, demand energy-efficient and high-performance hardware accelerators to support neural networks in resource-constrained environments. This paper presents a novel Multiply-Accumulate (MAC) unit based on Most Significant Digit First (MSDF) arithmetic, designed to address these challenges. The proposed MSDF MAC unit exploits digit-level parallelism and eliminates carry propagation delays to enhance throughput and reduce energy consumption. We integrate this unit into three different widely used applications: (I) Sparse Matrix-Vector Multiplication (SpMV), (II) Multi-Layer Perceptron (MLP), and (III) Denoising Autoencoder. All designs are synthesized using TSMC 45 nm CMOS technology, and the proposed designs achieve significant improvements, including 1.69× speedup and up to 60.4% energy reduction on SpMV, and at least 39% power savings on MLP with maintained accuracy for the MLP and the autoencoder. These results demonstrate the potential of MSDF-based accelerators for efficient neural network deployment on edge devices.

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Authors in the community:

Publication version

NA - Not Applicable

Publisher

IEEE

Link to the publisher's version

https://ieeexplore.ieee.org/document/11130344

Title of the publication container

2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

First page or article number

1

Last page

4

Volume

1

ISSN

2159-3477

DOI

10.1109/ISVLSI65124.2025.11130344

Fields of Science and Technology (FOS)

electrical-engineering-electronic-engineering-information-engineering - Electrical engineering, electronic engineering, information engineering

Keywords

  • MSDF arithmetic
  • hardware accelerators
  • edge computing
  • neural networks
  • energy efficiency

Publication language (ISO code)

eng - English

Rights type:

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