A Fast Mapping and Co-Design Toolchain for Stream-Based CGRAs

Martim Rendeiro Bento

Key information

Authors:

Martim Rendeiro Bento (Martim Rendeiro Bento)

Supervisors:

Pedro Filipe Zeferino Aidos Tomás (Pedro Filipe Zeferino Tomás); Nuno Filipe Valentim Roma (Nuno Filipe Valentim Roma)

Published in

December 2, 2025

Abstract

As computational demands continue to grow across key application domains, domain-specific accelerators (DSAs) have become a promising solution for achieving high performance with improved area and energy efficiency. Data streaming mechanisms further enhance these architectures by mitigating memory access bottlenecks and reducing resource overhead. However, the exploitation of this paradigm remains underutilized in existing DSA design frameworks. Moreover, current toolchains for stream-based DSA design are often poorly suited for architecture co-design, as they tend to be slow, lack crucial optimization features, or target different architectural classes. This thesis introduces a novel design space exploration (DSE) toolchain for the development of optimized data-streaming-based DSAs. The proposed approach targets a reconfigurable architecture comprising a mesh of processing elements (PEs) interconnected with dedicated streaming engines, enabling the decoupling of computation and memory access. It features a diverse set of tools for mapping applications, performing iterative hardware optimizations, and generating synthesizable PE array descriptions. The mapper, MIDAS, delivers results with similar quality to state-of-the-art tools while achieving up to 10,000x faster mapping times than exact methods and up to 73x faster than heuristic approaches. Meanwhile, the co-DSE tools automate pruning and optimization, producing designs with up to 4x area and 3x power improvements when synthesized, when compared to the initially generated arrays. Extensive evaluations validate the framework’s efficiency and scalability, establishing it as a comprehensive co-design environment for stream-based reconfigurable architectures.