Exploring processor frontend capabilities via micro-benchmarking

Rafael Abrantes Forte

Key information

Authors:

Rafael Abrantes Forte (Rafael Abrantes Forte)

Supervisors:

Aleksandar Ilic (Aleksandar Ilic); Leonel Augusto Pires Seabra de Sousa (Leonel Augusto Pires Seabra de Sousa)

Published in

January 20, 2021

Abstract

Nowadays, processor companies aim at achieving higher performing and more efficient processor ar-chitectures, which is not an easy task as we reach the limits of Moore’s Law. To keep up with themarket demands, processors micro-architectures are increasing in complexity, which makes it harder forapplication developers and other professionals to identify the factors that affect application efficiencyand performance. In order to accurately characterize and improve application performance, it is nec-essary to rely on models and tools that provide useful insights on how an application is performing onthe micro-processor. These models use micro benchmarking and hardware counters in order to obtaintheir the metrics, to guarantee more accurate results. Even though there are plenty of state-of-the artmodels used to analyse application performance, most of them focus on the Back End portion the themicro-architecture. Consequently, the Front End of the micro-architecture, which is responsible for thedecoding and issuing of instructions, has been overlooked. Which is an issue considering how it can im-pact and bottleneck application performance. In this Thesis a new methodology of micro-benchmarkingto assess Front End (FE) limitations is proposed, in order to provide useful insights on their impactin application performance. To achieve this goal, a set of micro benchmarks is designed using hardwarecounters and tested on the Intel Skylake micro-architecture to assess the Front End components and theircapabilities. Finally a set of benchmarks are created and used to validate the methodology proposed indifferent scenarios.